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HD6417750SBP200 参数 Datasheet PDF下载

HD6417750SBP200图片预览
型号: HD6417750SBP200
PDF下载: 下载PDF文件 查看货源
内容描述: 的SuperH RISC引擎 [SuperH RISC engine]
分类和应用: 外围集成电路时钟
文件页数/大小: 1039 页 / 6201 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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Transfer on channel 0  
Channel 0 is given the lowest  
priority.  
CH0 > CH1 > CH2 > CH3  
Initial priority order  
CH1 > CH2 > CH3 > CH0  
Priority order after transfer  
Transfer on channel 1  
When channel 1 is given the  
lowest priority, the priority of  
channel 0, which was higher  
than channel 1, is also  
Initial priority order  
CH0 > CH1 > CH2 > CH3  
shifted simultaneously.  
CH2 > CH3 > CH0 > CH1  
Priority order after transfer  
Transfer on channel 2  
When channel 2 is given the  
lowest priority, the priorities of  
channels 0 and 1, which were  
higher than channel 2, are  
also shifted simultaneously. If  
there is a transfer request for  
channel 1 only immediately  
afterward, channel 1 is given  
the lowest priority and the  
priorities of channels 3 and 0  
are simultaneously shifted  
down.  
Initial priority order  
CH0 > CH1 > CH2 > CH3  
Priority order after transfer  
CH3 > CH0 > CH1 > CH2  
CH2 > CH3 > CH0 > CH1  
Priority after transfer due to  
issuance of a transfer request  
for channel 1 only.  
Transfer on channel 3  
No change in priority order  
Initial priority order  
CH0 > CH1 > CH2 > CH3  
CH0 > CH1 > CH2 > CH3  
Priority order after transfer  
Figure 14.3 Round Robin Mode  
Figure 14.4 shows the changes in priority levels when transfer requests are issued simultaneously  
for channels 0 and 3, and channel 1 receives a transfer request during a transfer on channel 0. The  
operation of the DMAC in this case is as follows.  
Rev. 6.0, 07/02, page 516 of 986  
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