When DMA transfer is restarted, check whether a DMA transfer request is being held.
On-Chip Peripheral Module Request Mode: In this mode a transfer is performed in response to
a transfer request signal (interrupt request signal) from an on-chip peripheral module. As shown in
table 14.5, there are seven transfer request signals: input capture interrupts from the timer unit
(TMU), and receive-data-full interrupts (RXI) and transmit-data-empty interrupts (TXI) from the
two serial communication interfaces (SCI, SCIF). If DMA transfer is enabled (DE = 1, DME = 1,
TE = 0, NMIF = 0, AE = 0), transfer starts when a transfer request signal is input.
The source of the transfer request does not have to be the data transfer source or destination.
However, when the transfer request is set to RXI (transfer request by SCI/SCIF receive-data-full
interrupt), the transfer source must be the SCI/SCIF’s receive data register (SCRDR1/SCFRDR2).
When the transfer request is set to TXI (transfer request by SCI/SCIF transmit-data-empty
interrupt), the transfer destination must be the SCI/SCIF’s transmit data register
(SCTDR1/SCFTDR2).
Table 14.5 Selecting On-Chip Peripheral Module Request Mode with RS Bits
DMAC Transfer DMAC Transfer Transfer Transfer
RS3 RS2 RS1 RS0 Request Source Request Signal Source
Destination Bus Mode
1
0
0
0
SCI transmitter
SCTDR1 (SCI
transmit-data-
empty transfer
request)
External* SCTDR1
Cycle steal
mode
1
0
SCI receiver
SCRDR1 (SCI
receive-data-full
transfer request)
SCRDR1 External*
Cycle steal
mode
1
SCIF transmitter SCFTDR2 (SCIF External* SCFTDR2 Cycle steal
transmit-data-
empty transfer
request)
mode
1
SCIF receiver
SCFRDR2 (SCIF SCFRDR2 External*
receive-data-full
Cycle steal
mode
transfer request)
1
0
1
0
1
0
TMU channel 2
TMU channel 2
TMU channel 2
Input capture
occurrence
External* External*
Burst/cycle
steal mode
Input capture
occurrence
External* On-chip
Burst/cycle
steal mode
peripheral
Input capture
occurrence
On-chip
External*
Burst/cycle
steal mode
peripheral
TMU: Timer unit
SCI: Serial communication interface
SCIF: Serial communication interface with FIFO
Notes: 1. SCI/SCIF burst transfer setting is prohibited.
Rev. 6.0, 07/02, page 514 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
