Bit 7—Transmit Mode (TM): Specifies the bus mode for transfer.
Bit 7: TM
Description
0
1
Cycle steal mode
Burst mode
(Initial value)
Bits 6 to 4—Transmit Size 2 to 0 (TS2–TS0): These bits specify the transfer data size. For
external memory access, the setting of these bits serves as the access size in section 14.3,
Operation. For register access, the setting of these bits is the size in which the register is accessed.
Bit 6: TS2
Bit 5: TS1
Bit 4: TS0
Description
0
0
0
1
0
1
0
Quadword size (64-bit) specification(Initial value)
Byte size (8-bit) specification
1
0
Word size (16-bit) specification
Longword size (32-bit) specification
32-byte block transfer specification
1
Bit 3—Reserved: This bit is always read as 0, and should only be written with 0.
Bit 2—Interrupt Enable (IE): When this bit is set to 1, an interrupt request (DMTE) is generated
after the number of data transfers specified in DMATCR (when TE = 1).
Bit 2: IE
Description
0
Interrupt request not generated after number of transfers specified in
DMATCR
(Initial value)
1
Interrupt request generated after number of transfers specified in DMATCR
Rev. 6.0, 07/02, page 505 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
