14.2.5 DMA Operation Register (DMAOR)
Bit:
31
—
0
30
—
0
29
—
0
28
—
0
27
—
0
26
—
0
25
—
0
24
—
0
Initial value:
R/W:
R
R
R
R
R
R
R
R
Bit:
23
—
0
22
—
0
21
—
0
20
—
0
19
—
0
18
—
0
17
—
0
16
—
0
Initial value:
R/W:
R
R
R
R
R
R
R
R
Bit:
15
DDT
0
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
8
PR1
0
PR0
0
Initial value:
R/W:
R/W
R
R
R
R
R
R/W
R/W
Bit:
7
—
0
6
—
0
5
—
0
4
3
—
0
2
AE
1
0
COD
0
NMIF
0
DME
0
Initial value:
R/W:
0
R
R
R
R/(W)
R
R/(W)
R/(W)
R/W
Note: The AE and NMIF bits can only be written with 0 after being read as 1, to clear the flags.
The COD bit can be written to in the SH7750S only.
DMAOR is a 32-bit readable/writable register that specifies the DMAC transfer mode.
DMAOR is initialized to H'00000000 by a power-on or manual reset. They retain their values in
standby mode and deep sleep mode.
Bits 31 to 16—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 15—On-Demand Data Transfer (DDT): Specifies on-demand data transfer mode.
Bit 15: DDT
Description
0
1
Normal DMA mode
On-demand data transfer mode
(Initial value)
Note: %$9/ (DRAK0) is an active-high output in normal DMA mode. When the DDT bit is set to 1,
the %$9/ pin function is enabled and this pin becomes an active-low output.
Rev. 6.0, 07/02, page 507 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
