BE
EDOMODE
8/16/32/64-Bit Transfer
Single
32-Byte Transfer
Single
0
0
1
0
1
Setting prohibited
Single/fast page*
EDO
Setting prohibited
Fast page
1
EDO
Note: * In fast page mode, 32-bit or 64-bit transfer with a 16-bit bus, 64-bit transfer with a 32-bit
bus.
Bits 8 and 7—Memory Data Size (SZ1, SZ0): These bits specify the bus width of DRAM and
synchronous DRAM. This setting has priority over the BCR2 register setting.
Description
Bit 8: SZ1
Bit 7: SZ0
DRAM
SDRAM
0
0
1
0
1
64 bits
64 bits
Reserved (Setting prohibited) Reserved (Setting prohibited)
1
16 bits
32 bits
Reserved (Setting prohibited)
32 bits
Bits 6 to 3—Address Multiplexing (AMXEXT, AMX2–AMX0): These bits specify address
multiplexing for DRAM and synchronous DRAM. The address shift value is different for the
DRAM interface and the synchronous DRAM interface.
•
For DRAM Interface:
Description
Bit 6:
Bit 5:
Bit 4:
Bit 3:
AMXEXT
AMX2
AMX1
AMX0
DRAM
0*
0
0
0
8-bit column address product
(Initial value)
1
0
1
0
1
0
1
9-bit column address product
10-bit column address product
11-bit column address product
12-bit column address product
Reserved (Setting prohibited)
Reserved (Setting prohibited)
Reserved (Setting prohibited)
1
0
1
1
Note: * When the DRAM interface is used, clear the AMXEXT bit to 0.
Rev. 6.0, 07/02, page 357 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
