Bits 8 to 6—Address-2(/:( Assertion Delay (A6TED2–A6TED0): These bits set the delay
time from address output to 2(/:( assertion on the connected PCMCIA interface. The setting of
these bits is selected when the PCMCIA interface access TC bit is set to 1.
Bit 8: A6TED2
Bit 7: A6TED1
Bit 6: A6TED0
Waits Inserted
0
0
0
1
0
1
0
1
0
1
0 (Initial value)
1
1
0
1
2
3
1
6
9
12
15
Bits 5 to 3—2(/:( Negation-Address Delay (A5TEH2–A5TEH0): These bits set the address
hold delay time from 2(/:( negation in a write on the connected PCMCIA interface or in an I/O
card read. The setting of these bits is selected when the PCMCIA interface access TC bit is cleared
to 0.
Bit 5: A5TEH2
Bit 4: A5TEH1
Bit 3: A5TEH0
Waits Inserted
0
0
0
1
0
1
0
1
0
1
0 (Initial value)
1
1
0
1
2
3
1
6
9
12
15
Bits 2 to 0—2(/:( Negation-Address Delay (A6TEH2–A6TEH0): These bits set the address
hold delay time from 2(/:( negation in a write on the connected PCMCIA interface or in an I/O
card read. In the case of a memory card read, the address hold delay time from the data sampling
timing is set. The setting of these bits is selected when the PCMCIA interface access TC bit is set
to 1.
Rev. 6.0, 07/02, page 361 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
