Bits 15 and 14—PCMCIA Wait (A5PCW1, A5PCW0): These bits specify the number of waits
to be added to the number of waits specified by WCR2 in a low-speed PCMCIA wait cycle. The
setting of these bits is selected when the PCMCIA interface access TC bit is cleared to 0.
Bit 15: A5PCW1
Bit 14: A5PCW0
Waits Inserted
0
0
1
0
1
0 (Initial value)
15
30
50
1
Bits 13 and 12—PCMCIA Wait (A6PCW1, A6PCW0): These bits specify the number of waits
to be added to the number of waits specified by WCR2 in a low-speed PCMCIA wait cycle. The
setting of these bits is selected when the PCMCIA interface access TC bit is set to 1.
Bit 13: A6PCW1
Bit 12: A6PCW0
Waits Inserted
0
0
1
0
1
0 (Initial value)
15
30
50
1
Bits 11 to 9—Address-2(/:( Assertion Delay (A5TED2–A5TED0): These bits set the delay
time from address output to 2(/:( assertion on the connected PCMCIA interface. The setting of
these bits is selected when the PCMCIA interface access TC bit is cleared to 0.
Bit 11: A5TED2
Bit 10: A5TED1
Bit 9: A5TED0
Waits Inserted
0
0
0
1
0
1
0
1
0
1
0 (Initial value)
1
1
0
1
2
3
1
6
9
12
15
Rev. 6.0, 07/02, page 360 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
