exception are shown only for SSR, SPC, SGR, EXPEVT/INTEVT, SR, and PC, but other registers
may be set automatically by hardware, depending on the exception. For details, see section 5.6,
Description of Exceptions. Also, see section 5.6.4, Priority Order with Multiple Exceptions, for
exception handling during execution of a delayed branch instruction and a delay slot instruction,
and in the case of instructions in which two data accesses are performed.
Yes
Reset
requested?
No
Execute next instruction
Is highest-
priority exception
re-exception
type?
General
exception requested?
Yes
Yes
Cancel instruction execution
result
No
No
Yes
Interrupt
requested?
SSR ← SR
SPC ← PC
SGR ← R15
EXPEVT ← exception code
SR. {MD, RB, BL, FD, IMASK} ← 11101111
PC ← H'A000 0000
No
EXPEVT/INTEVT ← exception code
SR.{MD,RB,BL} ← 111
PC ← (BRCR.UBDE=1 && User_Break?
DBR: (VBR + Offset))
Figure 5.2 Instruction Execution and Exception Handling
Exception Source Acceptance
5.5.2
A priority ranking is provided for all exceptions for use in determining which of two or more
simultaneously generated exceptions should be accepted. Five of the general exceptions—the
general illegal instruction exception, slot illegal instruction exception, general FPU disable
exception, slot FPU disable exception, and unconditional trap exception—are detected in the
process of instruction decoding, and do not occur simultaneously in the instruction pipeline. These
exceptions therefore all have the same priority. General exceptions are detected in the order of
instruction execution. However, exception handling is performed in the order of instruction flow
(program order). Thus, an exception for an earlier instruction is accepted before that for a later
instruction. An example of the order of acceptance for general exceptions is shown in figure 5.3.
Rev. 6.0, 07/02, page 133 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
