5.3
Exception Handling Functions
5.3.1
Exception Handling Flow
In exception handling, the contents of the program counter (PC), status register (SR), and R15 are
saved in the saved program counter (SPC), saved status register (SSR), and saved general
register15(SGR), and the CPU starts execution of the appropriate exception handling routine
according to the vector address. An exception handling routine is a program written by the user to
handle a specific exception. The exception handling routine is terminated and control returned to
the original program by executing a return-from-exception instruction (RTE). This instruction
restores the PC and SR contents and returns control to the normal processing routine at the point at
which the exception occurred.
The SGR contents are not written back to R15 by an RTE instruction.
The basic processing flow is as follows. See section 2, Data Formats and Registers, for the
meaning of the individual SR bits.
1. The PC, SR, and R15 contents are saved in SPC, SSR, and SGR.
2. The block bit (BL) in SR is set to 1.
3. The mode bit (MD) in SR is set to 1.
4. The register bank bit (RB) in SR is set to 1.
5. In a reset, the FPU disable bit (FD) in SR is cleared to 0.
6. The exception code is written to bits 11–0 of the exception event register (EXPEVT) or
interrupt event register (INTEVT).
7. The CPU branches to the determined exception handling vector address, and the exception
handling routine begins.
5.3.2
Exception Handling Vector Addresses
The reset vector address is fixed at H'A000 0000. Exception and interrupt vector addresses are
determined by adding the offset for the specific event to the vector base address, which is set by
software in the vector base register (VBR). In the case of the TLB miss exception, for example,
the offset is H'0000 0400, so if H'9C08 0000 is set in VBR, the exception handling vector address
will be H'9C08 0400. If a further exception occurs at the exception handling vector address, a
duplicate exception will result, and recovery will be difficult; therefore, fixed physical addresses
(P1, P2) should be specified for vector addresses.
Rev. 6.0, 07/02, page 129 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
