5.4
Exception Types and Priorities
Table 5.2 shows the types of exceptions, with their relative priorities, vector addresses, and
exception/interrupt codes.
Table 5.2 Exceptions
Exception Execution
Category Mode
Priority Priority Vector
Exception
Offset Code
Exception
Level
Order Address
Reset
Abort type Power-on reset
Manual reset
1
1
1
1
1
2
1
3
H'A000 0000
—
—
—
—
H’000
H’020
H’000
H’140
H'A000 0000
H'A000 0000
H'A000 0000
H-UDI reset
Instruction TLB multiple-hit
exception
Data TLB multiple-hit exception
1
2
4
0
H'A000 0000
(VBR/DBR)
—
H’140
General
Re-
User break before instruction
H'100/— H'1E0
1
*
exception execution execution
type
Instruction address error
2
2
2
1
2
3
(VBR)
(VBR)
(VBR)
H'100
H'400
H'100
H'0E0
H'040
H'0A0
Instruction TLB miss exception
Instruction TLB protection
violation exception
General illegal instruction
exception
2
4
(VBR)
H'100
H'180
Slot illegal instruction exception
General FPU disable exception
Slot FPU disable exception
Data address error (read)
2
2
2
2
2
4
4
4
5
5
6
6
7
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
H'100
H'100
H'100
H'100
H'100
H'400
H'400
H'100
H'1A0
H'800
H'820
H'0E0
H'100
H'040
H'060
H'0A0
Data address error (write)
Data TLB miss exception (read) 2
Data TLB miss exception (write) 2
Data TLB protection
2
violation exception (read)
Data TLB protection
2
7
(VBR)
H'100
H'0C0
violation exception (write)
FPU exception
2
2
2
2
8
(VBR)
H'100
H'100
H'100
H'120
H'080
H'160
Initial page write exception
9
(VBR)
Completion Unconditional trap (TRAPA)
4
(VBR)
type
User break after instruction
10
(VBR/DBR)
H'100/— H'1E0
1
*
execution
Rev. 6.0, 07/02, page 130 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
