Pipeline flow:
Instruction n
TLB miss (data access)
EX MA WB
EX MA WB
IF
IF
ID
ID
Instruction n+1
General illegal instruction exception
TLB miss (instruction access)
Instruction n+2
IF
ID
IF
EX MA WB
IF: Instruction fetch
ID: Instruction decode
EX: Instruction execution
MA: Memory access
WB: Write-back
ID
EX MA WB
Instruction n+3
Order of detection:
General illegal instruction exception (instruction n+1) and
TLB miss (instruction n+2) are detected simultaneously
TLB miss (instruction n)
Order of exception handling:
TLB miss (instruction n)
Program order
1
Re-execution of instruction n
General illegal instruction exception
(instruction n+1)
2
Re-execution of instruction n+1
TLB miss (instruction n+2)
3
4
Re-execution of instruction n+2
Execution of instruction n+3
Figure 5.3 Example of General Exception Acceptance Order
Rev. 6.0, 07/02, page 134 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
