Table 5.2 Exceptions (cont)
Exception Execution
Category Mode
Priority Priority Vector
Exception
Offset Code
Exception
Level
Order
Address
Interrupt Completion Peripheral DMAC
DMTE0 4
*2
(VBR)
H'600 H'640
H'660
type
module
interrupt
(module/
source)
DMTE1
DMTE2
DMTE3
DMTE4
H'680
H'6A0
H'780
3
*
DMTE5
*
H'7A0
H'7C0
H'7E0
3
DMTE6
3
*
DMTE7
3
*
DMAE
ERI
H'6C0
H'700
H'720
H'740
H'760
SCIF
RXI
BRI
TXI
Priority: Priority is first assigned by priority level, then by priority order within each level (the lowest
number represents the highest priority).
Exception transition destination: Control passes to H'A000 0000 in a reset, and to [VBR + offset] in
other cases.
Exception code: Stored in EXPEVT for a reset or general exception, and in INTEVT for an interrupt.
IRL: Interrupt request level (pins IRL3–IRL0).
Module/source: See the sections on the relevant peripheral modules.
Notes: *1 When BRCR.UBDE = 1, PC = DBR. In other cases, PC = VBR + H'100.
*2 The priority order of external interrupts and peripheral module interrupts can be set by
software.
*3 SH7750R only.
5.5
Exception Flow
5.5.1
Exception Flow
Figure 5.2 shows an outline flowchart of the basic operations in instruction execution and
exception handling. For the sake of clarity, the following description assumes that instructions are
executed sequentially, one by one. Figure 5.2 shows the relative priority order of the different
kinds of exceptions (reset/general exception/interrupt). Register settings in the event of an
Rev. 6.0, 07/02, page 132 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
