5.6.1
Resets
(1) Power-On Reset
•
Sources:
SCK2 pin high level and 5(6(7 pin low level
When the watchdog timer overflows while the WT/,7 bit is set to 1 and the RSTS bit is
cleared to 0 in WTCSR. For details, see section 10, Clock Oscillation Circuits.
•
•
Transition address: H'A000 0000
Transition operations:
Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a
branch is made to PC = H'A000 0000.
In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD,
RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (I3–I0) are
set to B'1111.
CPU and on-chip peripheral module initialization is performed. For details, see the register
descriptions in the relevant sections. For some CPU functions, the 7567 pin and 5(6(7 pin
must be driven low. It is therefore essential to execute a power-on reset and drive the 7567
pin low when powering on.
If the SCK2 pin is changed to the low level while the 5(6(7 pin is low, a manual reset may
occur after the power-on reset operation. Do not drive the SCK2 pin low during this interval
(see figure 22.3).
Power_on_reset()
{
EXPEVT = H'00000000;
VBR = H'00000000;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
SR.(I0-I3) = B'1111;
SR.FD=0;
Initialize_CPU();
Initialize_Module(PowerOn);
PC = H'A0000000;
}
Rev. 6.0, 07/02, page 136 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
