SERIAL I/O
11.2 Block description
(1) Interrupt priority level select bits (bits 0 to 2)
These bits select a priority level of the UARTi transmit interrupt or UARTi receive interrupt. When
using UARTi transmit/receive interrupts, select one of the priority levels (1 to 7). When a UARTi
transmit/receive interrupt request occurs, its priority level is compared with the processor interrupt
priority level (IPL). The requested interrupt is enabled only when its priority level is higher than the
IPL. (However, this applies when the interrupt disable flag (I) = “0.”) To disable UARTi transmit/
receive interrupts, be sure to set these bits to “000 ” (level 0).
2
(2) Interrupt request bit (bit 3)
The UARTi transmit interrupt request bit is set to “1” when data has been transferred from the UARTi
transmit buffer register to the UARTi transmit register.
The UARTi receive interrupt request bit functions as below:
ꢀ When receive interrupt is selected (bit 5 = 0 at addresses 3416, 3C16
)
The UARTi receive interrupt request bit is set to “1” when data has been transferred from the
UARTi receive register to the UARTi receive buffer register.
(However, the UARTi receive interrupt request bit does not change when an overrun error has
occurred.)
ꢀ When receive error interrupt is selected (bit 5 = 1 at addresses 3416, 3C16
)
The UARTi receive interrupt request bit is set to “1” when an error (an overrun error in the clock
synchronous serial I/O mode; an overrun error, framing error, or parity error in UART mode) has
occurred.
Each interrupt request bit is automatically cleared to “0” when its corresponding interrupt request has
been accepted. This bit can be set to “1” or cleared to “0” by software.
7906 Group User’s Manual Rev.2.0
11-16
RENESAS [ RENESAS TECHNOLOGY CORP ]
