SERIAL I/O
11.2 Block description
The UARTi receive register is used to convert serial data, which is input to the RxD
i
pin, into parallel data.
This register takes in the signal input to the RxD pin, bit by bit, synchronously with the transfer clock.
i
The UARTi receive buffer register is used to read out receive data. When reception has been completed,
the receive data taken in the UARTi receive register is automatically transferred to the UARTi receive
buffer register. Note that the contents of the UARTi receive buffer register is updated when the next data
has been ready in the UARTi receive register before the data transferred to the UARTi receive buffer
register is read out. (i.e., an overrun error occurs.)
When “MSB first” is selected in the clock synchronous serial I/O mode, bit position of data in the UARTi
receive buffer register is reversed, and then the data of which bit position was reversed will be read out
as receive data. (Refer to section “11.3.2 Transfer data format.”) Receive operation itself is the same
whichever format is selected, “LSB first” or “MSB first.”
The UARTi receive buffer register is initialized by setting the receive enable bit (bit 2 at addresses 3516
3D16) to “1” after clearing it to “0.”
,
Figure 11.2.9 shows the contents of the UARTi receive buffer register at reception completed.
Low-order byte
High-order byte
(addresses 3616, 3E16
)
(addresses 3716, 3F16
)
b7
b0 b7
b0
UART mode
(Transfer data length : 9 bits)
0
0
0
0
0
0
0
0
0
0
0
0
0
Receive data (9 bits)
Receive data (8 bits)
Receive data (7 bits)
Clock synchronous
serial I/O mode,
UART mode
0
0
0
(Transfer data length : 8 bits)
Same value as bit
7 in low-order byte
UART mode
(Transfer data length : 7 bits)
0
0 0 0 0
Same value as bit
6 in low-order byte
Fig. 11.2.9 Contents of UARTi receive buffer register at reception completed
7906 Group User’s Manual Rev.2.0
11-13
RENESAS [ RENESAS TECHNOLOGY CORP ]
