SERIAL I/O
11.3 Clock synchronous serial I/O mode
11.3 Clock synchronous serial I/O mode
Table 11.3.1 lists the performance overview in the clock synchronous serial I/O mode, and Table 11.3.2 lists
the functions of I/O pins in this mode.
Table 11.3.1 Performance overview in clock synchronous serial I/O mode
Item
Transfer data format
Functions
Transfer data has a length of 8 bits.
LSB first or MSB first can be selected by software.
BRGi’s output divided by 2
Transfer rate
When selecting internal clock
When selecting external clock
Maximum 5 Mbps
Transmit/Receive control
CTS function or RTS function can be selected by software.
Table 11.3.2 Functions of I/O pins in clock synchronous serial I/O mode
Pin name
(P1 , P1
Functions
Method of selection
switch bit = “0”
TxD
i
3
7
)
Serial data output pin TxD
0
/P1
3
or TxD
1
/P1
7
(Dummy data is output when performing only reception.) (Note)
Programmable I/O port pin TxD /P1 or TxD /P1 switch bit = “1”
Serial data input pin Port P1 direction register’s corresponding bit = “0”
0
3
1
7
RxD
CLK
i
i
(P1
(P1
2
1
, P1
, P1
6
)
)
Programmable I/O port pin – (Can be used as an I/O port pin when performing only transmission.)
Transfer clock output pin Internal/External clock select bit = “0”
5
Transfer clock input pin Internal/External clock select bit = “1”
CTS
i
, RTS
i
CTS input pin
See Table 11.2.1.
(P1 , P1
0
1, P1
4
, P1
5
) RTS output pin
Programmable I/O port
Port P1 direction register: address 0516
Internal/External clock select bit: bit 3 at addresses 3016, 3816
TxD
TxD
0
/P1
/P1
3
switch bit: bit 2 at address AC16
switch bit: bit 3 at address AC16
1
7
Note: The TxD pin outputs “H” level until transmission starts after UARTi’s operating mode is selected.
i
11.3.1 Transfer clock (Synchronizing clock)
Data transfer is performed synchronously with a transfer clock. For the transfer clock, the following selection
is possible:
ꢀ Whether to generate a transfer clock internally or to input it from the external.
ꢀ Polarity of transfer clock.
The transfer clock is generated by operation of the transmit control circuit. Accordingly, even when performing
only reception, set the transmit enable bit to “1,” and set dummy data in the UARTi transmit buffer register
in order to make the transmit control circuit active.
(1) Internal generation of transfer clock
The count source selected with the BRG count source select bits is divided by the BRGi, and the
BRGi output is further divided by 2. This divided output is the transfer clock. The transfer clock is
output from the CLK
i
pin.
Transfer clock’s frequency =
fi
f
i
: Frequency of BRGi’s count source (f
2
, f16, f64, or f512)
2 (n+1)
n: Setting value of BRGi
7906 Group User’s Manual Rev.2.0
11-20
RENESAS [ RENESAS TECHNOLOGY CORP ]
