SERIAL I/O
11.2 Block description
11.2.5 UARTi receive register and UARTi receive buffer register
Figure 11.2.7 shows the block diagram of the receiver; Figure 11.2.8 shows the structure of UARTi receive
buffer register.
Data bus (odd)
Data bus (even)
UARTi receive
buffer register
0
0
0
0
0
0
0
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
SP : Stop bit
PAR : Parity bit
8-bit UART
9-bit UART
Clock sync.
Parity
enabled
9-bit UART
2SP
1SP
UART
SP
SP
PAR
RxD
i
Parity
disabled
Clock sync.
7-bit UART
7-bit UART
UARTi receive register
8-bit UART
Clock sync.
Fig. 11.2.7 Block diagram of receiver
(b8)
b0 b7
(b15)
b7
b0
UART0 receive buffer register (Addresses 3716, 3616
UART1 receive buffer register (Addresses 3F16, 3E16
)
)
Function
Bit
At reset R/W
Undefined RO
8 to 0 Receive data is read out from here.
15 to 9 The value is “0” at reading.
0
—
Fig. 11.2.8 Structure of UARTi receive buffer register
7906 Group User’s Manual Rev.2.0
11-12
RENESAS [ RENESAS TECHNOLOGY CORP ]
