SERIAL I/O
11.2 Block description
11.2.9 Port P8 direction register
I/O pins for serial I/O are multiplexed with port P1 pins. When using pins P1
1
, P1
2
, P1
5
, and P1 as serial
6
I/O’s input pins (CTS
to set these pins for the input mode. When using these pins as other serial I/O’s pins (CTS
TxD ), these pins are forcibly set as I/O pins for serial I/O regardless of the port P8 direction register’s
i
, RxD
i
), clear the corresponding bits of the port P1 direction register to “0” in order
i
/RTS , CLK
i
i
,
i
contents. Figure 11.2.14 shows the relationship between the port P1 direction register and serial I/O’s
I/O pins. For details, refer to the description of each operating mode.
b7 b6 b5 b4 b3 b2 b1 b0
Port P1 direction register (Address
516)
Bit
0
Corresponding pin name
Function
At reset
R/W
RW
RW
RW
RW
RW
RW
RW
RW
Pin CTS0/RTS0
Pin CTS0/CLK0
Pin RxD0
0
0
0
0
0
0
0
0
0 : Input mode
1 : Output mode
1
2
When using pins P11, P12, P15, and P16 as serial
I/O’s input pins (CTS0, RxD0, CTS1, RxD1), clear
the corresponding bits to “0.”
3
Pin TxD0
4
Pin CTS1/RTS1
Pin CTS1/CLK1
Pin RxD1
5
6
7
Pin TxD1
Fig. 11.2.14 Relationship between port P1 direction register and serial I/O’s I/O pins
7906 Group User’s Manual Rev.2.0
11-18
RENESAS [ RENESAS TECHNOLOGY CORP ]
