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7906 参数 Datasheet PDF下载

7906图片预览
型号: 7906
PDF下载: 下载PDF文件 查看货源
内容描述: 16位单片机 [16-BIT SINGLE-CHIP MICROCOMPUTER]
分类和应用: 计算机
文件页数/大小: 531 页 / 3056 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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SERIAL I/O  
11.2 Block description  
11.2.6 UARTi baud rate register (BRGi)  
The UARTi baud rate register (BRGi) is an 8-bit timer exclusively used for UARTi to generate a transfer  
clock. It has a reload register. Assuming that the value set in the BRGi is n(n = 0016to FF16), the BRGi  
divides the count source frequency by (n + 1).  
In the clock synchronous serial I/O mode, the BRGi is valid when an internal clock is selected, and the  
BRGis output divided by 2 becomes the transfer clock. In the UART mode, the BRGi is always valid, and  
the BRGis output divided by 16 becomes the transfer clock.  
The data written to the BRGi is written to both the timer and the reload register whichever transmission/  
reception is in progress or not. Accordingly, writing to these register must be performed while transmission/  
reception halts.  
Figure 11.2.10 shows the structure of the UARTi baud rate register (BRGi); Figure 11.2.11 shows the block  
diagram of transfer clock generating section.  
b7  
b0  
UART0 baud rate register (BRG0) (Address 3116  
UART1 baud rate register (BRG1) (Address 3916  
)
)
Bit  
Function  
At reset R/W  
Any value in the range from 0016to FF16can be set.  
Assuming that the set value = n, BRGi divides the count source frequency by (n + 1).  
Undefined WO  
7 to 0  
Note: Writing to this register must be performed while the transmission/reception halts.  
Use the MOVM (MOVMB) or STA (STAB, STAD) instruction for writing to this register.  
Fig. 11.2.10 Structure of UARTi baud rate register (BRGi)  
<Clock synchronous serial I/O mode>  
1/2  
f
i
BRGi  
Transmit control circuit  
Receive control circuit  
Transfer clock for transmit operation  
Transfer clock for receive operation  
f
EXT  
<UART mode>  
Transmit control circuit  
Receive control circuit  
Transfer clock for transmit operation  
Transfer clock for receive operation  
1/16  
1/16  
f
i
BRGi  
f
EXT  
f
i
: Clock selected by BRG count source select bits (f  
2
, f16, f64, or f512)  
fEXT : Clock input to CLK pin (external clock)  
i
Fig. 11.2.11 Block diagram of transfer clock generating section  
7906 Group Users Manual Rev.2.0  
11-14  
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