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VRS51L1050-25-PG-ISPV3 参数 Datasheet PDF下载

VRS51L1050-25-PG-ISPV3图片预览
型号: VRS51L1050-25-PG-ISPV3
PDF下载: 下载PDF文件 查看货源
内容描述: 的Versa 8051 MCU的3.3V与IAP / ISP功能的Flash 64KB [Versa 8051 3.3V MCU with 64KB of IAP/ISP Flash]
分类和应用: 光电二极管微控制器
文件页数/大小: 49 页 / 505 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
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VRS51L1050  
RB8, and to set RI, will be generated if, and only if, the  
following conditions are met at the time the final shift  
pulse is generated:  
UART Operation in Mode 3  
In Mode 3, 11 bits are transmitted (through TXD) or  
received (through RXD). The transactions are  
composed of: a start bit (low), 8 data bits (LSB first), a  
programmable 9th data bit and one stop bit (high).  
o
o
Either SM2 = 0 or the received stop bit = 1  
RI = 0  
If both conditions are met, the stop bit enters RB8, the  
8 data bits go into SBUF and RI is activated. If one of  
these conditions is not met, the received frame is  
completely lost. At this time, whether the above  
conditions are met or not, the unit returns to searching  
for a 1 to 0 transition in RXD.  
Mode 3 is identical to Mode 2 in all respects but one:  
the baud rate. Either Timer 1 or Timer 2 generates the  
baud rate in Mode 3.  
FIGURE 20: SERIAL PORT MODE 3 BLOCK DIAGRAM  
Internal Bus  
1
Write to  
SBUF  
UART Operation in Mode 2  
Timer 1  
Overflow  
In Mode 2 a total of 11 bits are transmitted (through  
TXD) or received (through RXD). The transactions are  
composed of: a start bit (low), 8 data bits (LSB first), a  
programmable 9th data bit and one stop bit (high).  
For transmission, the 9th data bit comes from the TB8  
bit of SCON. For example, the parity bit P in the PSW  
could be moved into TB8. For reception, the 9th data bit  
is automatically written into RB8 of the SCON register.  
Q
S
D
SBUF  
TXD  
CLK  
Timer 2  
Overflow  
ZERO DETECTOR  
÷2  
0
1
Shift  
Start  
Data  
SMOD  
0
0
1
TX Control Unit  
TCLK  
TX Clock  
÷16  
Send  
÷16  
TI  
1
RCLK  
Serial Port  
Interrupt  
RI  
SAMPLE  
RX Clock  
Start  
Load  
SBUF  
RX Control Unit  
1-0 Transition  
Detector  
In Mode 2, the baud rate is programmable to either  
1/32 or 1/64 the oscillator frequency.  
SHIFT  
Bit  
Detector  
9-Bit Shift Register  
Shift  
RXD  
FIGURE 19: SERIAL PORT MODE 2 BLOCK DIAGRAM  
LOAD SBUF  
Internal Bus  
1
Write to  
SBUF  
SBUF  
READ SBUF  
Internal Bus  
Q
S
D
SBUF  
Fosc/2  
÷2  
TXD  
CLK  
ZERO DETECTOR  
0
1
Shift  
Data  
Stop  
Start  
SMOD  
TX Control Unit  
TX Clock  
Send  
÷16  
TI  
÷16  
Serial Port  
Interrupt  
Sample  
RI  
RX Clock  
Control  
Load  
SBUF  
RX Control Unit  
1-0 Transition  
Detector  
Start  
SHIFT  
Bit  
Detector  
9-Bit Shift Register  
Shift  
RXD  
LOAD SBUF  
SBUF  
READ SBUF  
Internal Bus  
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