VRS51L1050
UART Reception in Mode 2 and Mode 3
UART in Mode 2 and 3: Additional Information
One to 0 transitions on the RXD pin initiate reception.
For this reason, RXD is sampled at a rate of 16
multiplied by the established baud rate. When a
transition is detected, the 1FFh is written into the input
shift register and the divide-by-16 counter is
immediately reset.
As mentioned previously, for an operation in modes 2
and 3, 11 bits are transmitted (through TXD) or
received (through RXD). The signal comprises: a
logical low start bit, 8 data bits (LSB first), a
programmable 9th data bit, and one logical high stop
bit.
During the 7th, 8th and 9th counter states of each bit
time, the bit detector samples the value of RXD. The
accepted value is the value that was seen in at least
two of the three samples. If the value accepted during
the first bit time is not zero, the receive circuits are
reset and the unit goes back to searching for another 1
to 0 transition. If the start bit is valid, it is shifted into
the input shift register, and the reception of the rest of
the frame will proceed.
On transmit, (TB8 in SCON) can be assigned the value
of 0 or 1. On receive, the 9th data bit enters RB8 in
SCON. The baud rate is programmable to either 1/32
or 1/64 the oscillator frequency in Mode 2. Mode 3 may
have a variable baud rate generated from either Timer
1 or Timer 2 depending on the states of TCLK and
RCLK.
UART Transmission in Mode 2 and Mode 3
For a receive operation, the data bits come in from the
right as 1’s shift out on the left. As soon as the start bit
arrives at the leftmost position in the shift register (9-bit
register), it instructs the RX control block to do one
more shift, to set RI and to load SBUF and RB8. The
signal to set RI and to load SBUF and RB8 will be
generated if, and only if, the following conditions are
satisfied at the instance when the final shift pulse is
generated:
The transmission is initiated by any instruction that
makes use of SBUF as the destination register. The 9th
bit position of the transmit shift register is loaded by the
“write to SBUF” signal. This event also informs the
UART transmission control unit that a transmission has
been requested. After the next rollover in the divide-by-
16 counter, a transmission actually starts at the
beginning of the machine cycle. It follows that the bit
times are synchronized to the divide-by-16 counter and
not to the “write to SBUF” signal, as in the previous
mode.
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Either SM2 = 0 or the received 9th bit = 1
RI = 0
If both conditions are met, the 9th data bit received
enters RB8, and the first 8 data bits enter SBUF. If one
of these conditions is not met, the received frame is
completely lost. One bit time later, whether the above
conditions are met or not, the unit returns to searching
for a 1 to 0 transition at the RXD input.
Transmissions begin when the SEND signal is
activated, which places the start bit on the TXD pin.
Data is activated one bit time later. This activation
enables the output bit of the transmit shift register to
the TXD pin. The first shift pulse occurs one bit time
after that.
The first shift clocks a stop bit (1) into the 9th bit
position of the shift register on TXD. Thereafter, only
zeros are clocked in. Thus, as data bits shift out to the
right, zeros are clocked in from the left. When TB8 is at
the output position of the shift register, the stop bit is
just to the left of TB8, and all positions to the left of that
contain zeros. This condition signals to the TX control
unit to shift one more time and set TI, while
deactivating SEND. This occurs at the 11th divide-by-
16 rollover after “write to SBUF”.
Please note that the value of the received stop bit is
unrelated to SBUF, RB8 or RI.
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