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Internet Data Sheet
HYB18T512161B2F–20/25
512-Mbit Double-Data-Rate-Two SDRAM
TABLE 4
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
Low Voltage CMOS
LV-CMOS
CMOS
OD
CMOS Levels
Open Drain. The corresponding ball has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
FIGURE 1
Chip Configuration, PG-TFBGA-84 (top view)
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Notes
2. LDM is the data mask signal for DQ[7:0], UDM is the data
mask signal for DQ[15:8]
3. VDDL and VSSDL are power and ground for the DLL. VDDL is
1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is
data strobe for DQ[7:0]
connected to VDD on the device. VDD, VDDQ, VSSDL, VSS
and VSSQ are isolated on the device.
,
Rev. 1.1, 2007-06
8
05152007-ZYAH-ACMZ
Date: 2008-02-26
QIMONDA [ QIMONDA AG ]
