Internet Data Sheet
HYB18T512161B2F–20/25
512-Mbit Double-Data-Rate-Two SDRAM
1.2
Description
The 512-Mb DDR2 DRAM is a high-speed Double-Data-
Rate-Two CMOS DRAM device containing 536,870,912 bits
and internally configured as a quad-bank DRAM. The 512-Mb
device is organized as 8 Mbit × 16 I/O × 4 banks chip. These
devices achieve high speed transfer rates starting at
800 Mb/sec/pin for general applications.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS-DQS pair in a source synchronous
fashion.
The device is designed to comply with all DDR2 DRAM key
features:
A 15-bit address bus is used to convey row, column and bank
address information in a RAS-CAS multiplexing style.
1. posted CAS with additive latency,
2. write latency = read latency - 1,
An Auto-Refresh and Self-Refresh mode is provided along
with various power-saving power-down modes.
3. normal and weak strength data-output driver,
4. Off-Chip Driver (OCD) impedance adjustment
5. On-Die Termination (ODT) function.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
The DDR2 SDRAM is available in P-TFBGA package.
Rev. 1.1, 2007-06
4
05152007-ZYAH-ACMZ
Date: 2008-02-26
QIMONDA [ QIMONDA AG ]
