Internet Data Sheet
HYB18T512161B2F–20/25
512-Mbit Double-Data-Rate-Two SDRAM
Ball#
Name
Ball
Type
Buffer
Type
Function
B3
F3
UDM
LDM
I
I
SSTL
SSTL
Data Mask Upper/Lower Byte
Note: LDM and UDM are the input mask signals and control the
lower or upper bytes.
Power Supplies
A9,C1,C3,C7,C9
A1
VDDQ
VDD
PWR
PWR
PWR
PWR
–
–
–
–
I/O Driver Power Supply
Power Supply
A7,B2,B8,D2,D8
A3,E3
VSSQ
VSS
I/O Driver Power Supply
Power Supply
Power Supplies
J2
VREF
VDDQ
VDDL
VDD
AI
–
–
–
–
–
–
–
I/O Reference Voltage
I/O Driver Power Supply
Power Supply
E9, G1, G3, G7, G9
J1
PWR
PWR
PWR
PWR
PWR
PWR
E1, J9, M9, R1
E7, F2, F8, H2, H8
J7
Power Supply
VSSQ
VSSDL
VSS
I/O Driver Power Supply
Power Supply
A3, E3,J3,N1,P9
Not Connected
Power Supply
A2, E2, R3, R7, R8, L1 NC
NC
I
–
Not Connected
Other Balls
K9
ODT
SSTL
On-Die Termination Control
Note: ODT is applied to each DQ, UDQS, UDQS, LDQS, LDQS,
UDM and LDM signal. An EMRS(1) control bit enables or
disables the ODT functionality.
TABLE 3
Abbreviations for Ball Type
Abbreviation
Description
I
Standard input-only ball. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
O
I/O
AI
PWR
GND
NC
Ground
Not Connected
Rev. 1.1, 2007-06
7
05152007-ZYAH-ACMZ
Date: 2008-02-26
QIMONDA [ QIMONDA AG ]
