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Internet Data Sheet
HYB18T512161B2F–20/25
512-Mbit Double-Data-Rate-Two SDRAM
Field
Bits
Type1)
Description
Burst Type
BT
3
w
0B
1B
BT Sequential
BT Interleaved
BL
[2:0]
w
Burst Length
Note: All other bit combinations are illegal.
010B BL 4
011B BL 8
1) w = write only register bits
2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and
rounding up to the next integer: WR [cycles] ≥ tWR (ns) / tCK (ns). The mode register must be programmed to fulfill the minimum requirement
for the analogue tWR timing WRMIN is determined by tCK.MAX and WRMAX is determined by tCK.MIN
.
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TABLE 7
Extended Mode Register Definition (BA[1:0] = 01B)
Field
Bits
Type1)
Description
Bank Address [1]
BA1
14
reg. addr.
0B
BA1 Bank Address
BA0
Qoff
13
12
Bank Address [0]
1B
BA0 Bank Address
w
Output Disable
0B
1B
QOff Output buffers enabled
QOff Output buffers disabled
DQS
OCD
10
Complement Data Strobe (DQS Output)
0B
1B
DQS Enable
DQS Disable
[9:7]
Off-Chip Driver Calibration Program
000B OCD OCD calibration mode exit, maintain setting
001B OCD Drive (1)
Program
010B OCD Drive (0)
100B OCD Adjust mode
111B OCD OCD calibration default
Rev. 1.1, 2007-06
11
05152007-ZYAH-ACMZ
Date: 2008-02-26
QIMONDA [ QIMONDA AG ]
