Internet Data Sheet
HYB18T512161B2F–20/25
512-Mbit Double-Data-Rate-Two SDRAM
Field
Bits
Type1)
Description
AL
[5:3]
Additive Latency
Note: All other bit combinations are illegal.
000B AL 0
001B AL 1
010B AL 2
011B AL 3
100B AL 4
101B AL 5
110B AL 6
RTT
6,2
Nominal Termination Resistance of ODT
00B RTT ∞ (ODT disabled)
01B RTT 75 Ohm
10B RTT 150 Ohm
11B RTT 50 Ohm
DIC
DLL
1
0
Off-chip Driver Impedance Control
0B
1B
DIC Full (Driver Size = 100%)
DIC Reduced
DLL Enable
0B
1B
DLL Enable
DLL Disable
1) w = write only register bits
$ꢂꢂ
$ꢂꢁ
ꢁ
$ꢈ
$ꢇ
$ꢆ
$ꢄ
$ꢊ
$ꢉ
$ꢅ
$ꢃ
$ꢂ
$ꢁ
%$ꢂ
ꢂ
%$ꢁ
ꢁ
$ꢂꢃ
65)
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢁ
3$65
UHJꢌꢀDGGU
TABLE 8
EMRS(2) Programming Extended Mode Register Definition (BA[1:0]=10B)
Description
reg. addr., Bank Address [1]
Field Bits
Type1)
BA1
BA0
A
14
1B
BA1 Bank Address
13
Bank Address [0]
0B
BA0 Bank Address
[12:8]
7
w
w
Address Bus
00000B
A Address bits
SRF
Address Bus, High Temperature Self Refresh Rate for TCASE > 85°C
0B
1B
A7 disable
A7 enable 2)
A
[6:3]
w
Address Bus
0000B A Address bits
Rev. 1.1, 2007-06
12
05152007-ZYAH-ACMZ
Date: 2008-02-26
QIMONDA [ QIMONDA AG ]
