Internet Data Sheet
HYB18T512161B2F–20/25
512-Mbit Double-Data-Rate-Two SDRAM
2
Configuration
2.1
Chip Configuration
The chip configuration of a DDR2 SDRAM is listed by function in Table 2. The abbreviations used in the Ball# and Buffer Type
columns are explained in Table 3 and Table 4 respectively. The ball numbering for the FBGA package is depicted in Figure 1.
TABLE 2
Chip Configuration of DDR2 SDRAM
Ball#
Name
Ball
Type
Buffer
Type
Function
Clock Signals
J8
CK
CK
I
I
SSTL
SSTL
Clock Signal CK, Complementary Clock Signal CK
Note: CK and CK are differential system clock inputs. All address
and control inputs are sampled on the crossing of the
positive edge of CK and negative edge of CK. Output (read)
data is referenced to the crossing of CK and CK (both
direction of crossing)
K8
K2
CKE
I
SSTL
Clock Enable
Note: CKE HIGH activates and CKE LOW deactivates internal
clock signals and device input buffers and output drivers.
Taking CKE LOW provides Precharge Power-Down and
Self-Refresh operation (all banks idle), or Active Power-
Down (row Active in any bank). CKE is synchronous for
power down entry and exit and for self-refresh entry. Input
buffers excluding CKE are disabled during self-refresh.
CKE is used asynchronously to detect self-refresh exit
condition. Self-refresh termination itself is synchronous.
After VREF has become stable during power-on and
initialisation sequence, it must be maintained for proper
operation of the CKE receiver. For proper self-refresh entry
and exit, VREF must be maintained to this input. CKE must
be maintained HIGH throughout read and write accesses.
Input buffers, excluding CK, CK, ODT and CKE are
disabled during power-down
Control Signals
K7
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
L7
K3
L8
CS
Chip Select
Address Signals
Rev. 1.1, 2007-06
5
05152007-ZYAH-ACMZ
Date: 2008-02-26
QIMONDA [ QIMONDA AG ]
