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Internet Data Sheet
HYB18T512161B2F–20/25
512-Mbit Double-Data-Rate-Two SDRAM
Field Bits
Type1)
Description
Partial Self Refresh for 4 banks
PASR [2:0]
w
Address Bus, Partial Array Self Refresh for 4 Banks3)
000B PASR0 Full Array
001B PASR1 Half Array (BA[1:0]=00, 01)
010B PASR2 Quarter Array (BA[1:0]=00)
011B PASR3 Not defined
100B PASR4 3/4 array (BA[1:0]=01, 10, 11)
101B PASR5 Half array (BA[1:0]=10, 11)
110B PASR6 Quarter array (BA[1:0]=11)
111B PASR7 Not defined
1) w = write only
2) When DRAM is operated at 85°C ≤ TCase ≤ 95°C the extended self refresh rate must be enabled by setting bit A7 to "1" before the self
refresh mode can be entered.
3) If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost if self refresh
is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued
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TABLE 9
EMR(3) Programming Extended Mode Register Definition (BA[1:0]=10B)
Description
Bank Adress[1]
Field
Bits
Type1)
BA1
14
1B
BA1 Bank Address
BA0
A
13
Bank Adress[0]
1B
BA0 Bank Address
[12:0]
w
Address Bus[12:0]
0B
A[12:0] Address bits
1) w = write only
TABLE 10
ODT Truth Table
Input Pin
EMRS(1) Address Bit A10
EMRS(1) Address Bit A11
DQ[7:0]
DQ[15:8]
LDQS
X
X
X
0
LDQS
X
X
UDQS
UDQS
X
0
Rev. 1.1, 2007-06
13
05152007-ZYAH-ACMZ
Date: 2008-02-26
QIMONDA [ QIMONDA AG ]
