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HYB18T512161B2F-25 参数 Datasheet PDF下载

HYB18T512161B2F-25图片预览
型号: HYB18T512161B2F-25
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX16, 0.5ns, CMOS, PBGA84, ROHS COMPLIANT, PLASTIC, TFBGA-84]
分类和应用: 时钟动态存储器双倍数据速率内存集成电路
文件页数/大小: 37 页 / 1297 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYB18T512161B2F–20/25  
512-Mbit Double-Data-Rate-Two SDRAM  
Input Pin  
EMRS(1) Address Bit A10  
EMRS(1) Address Bit A11  
LDM  
UDM  
X
X
Note: X = don’t care; 0 = bit set to low; 1 = bit set to high  
TABLE 11  
Burst Length and Sequence  
Burst Length  
Starting Address  
(A2 A1 A0)  
Sequential Addressing  
(decimal)  
Interleave Addressing  
(decimal)  
4
x 0 0  
x 0 1  
x 1 0  
x 1 1  
0 0 0  
0 0 1  
0 1 0  
0 1 1  
1 0 0  
1 0 1  
1 1 0  
1 1 1  
0, 1, 2, 3  
0, 1, 2, 3  
1, 2, 3, 0  
1, 0, 3, 2  
2, 3, 0, 1  
2, 3, 0, 1  
3, 0, 1, 2  
3, 2, 1, 0  
8
0, 1, 2, 3, 4, 5, 6, 7  
1, 2, 3, 0, 5, 6, 7, 4  
2, 3, 0, 1, 6, 7, 4, 5  
3, 0, 1, 2, 7, 4, 5, 6  
4, 5, 6, 7, 0, 1, 2, 3  
5, 6, 7, 4, 1, 2, 3, 0  
6, 7, 4, 5, 2, 3, 0, 1  
7, 4, 5, 6, 3, 0, 1, 2  
0, 1, 2, 3, 4, 5, 6, 7  
1, 0, 3, 2, 5, 4, 7, 6  
2, 3, 0, 1, 6, 7, 4, 5  
3, 2, 1, 0, 7, 6, 5, 4  
4, 5, 6, 7, 0, 1, 2, 3  
5, 4, 7, 6, 1, 0, 3, 2  
6, 7, 4, 5, 2, 3, 0, 1  
7, 6, 5, 4, 3, 2, 1, 0  
Notes  
2. Order of burst access for sequential addressing is “nibble-  
based” and therefore different from SDR or DDR  
components  
1. PageSize and Length is a function of I/O  
organization:32Mb (CA[9:0]); Page Size = 2 kByte; Page  
Length = 1024  
Rev. 1.1, 2007-06  
14  
05152007-ZYAH-ACMZ  
Date: 2008-02-26  
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