HYB18H512321AF
512-Mbit GDDR3
Electrical Characteristics
Table 38
Timing Parameters (HYB18H512321AF–12/14/16/20)
Parameter
CAS
latency
Symbol
Limit Values
–16
Unit
–20
–12
–14
min max min max min max min
max
20
—
20
—
20
—
20
—
Rev. ID EMRS to DQ on timing tRIDon
ns
ns
—
20
—
20
—
20
—
20
REV. ID EMRS to DQ off
tRIDoff
timing
1) DLLon mode
2) tHP is the lesser of tCL minimum and tCH minimum actually applied to the device CLK, CLK inputs
3) This value of tMRD applies only to the case where the ’DLL reset ’ bit is not activated.
4) tMRD is defined from MRS to any other command then READ.
5) tRAS,max is 8*tREFi
6) tCCD is either for gapless consecutive reads or gapless consecutive writes. BL =4
7) WTR and tWR start at the first rising edge of CLK after the last valid (falling) WDQS edge of the slowest WDQS signal.
8) Please round up tRTW to the next integer of tCK.
9) This parameter is defined per byte.
Data Sheet
94
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
