HYB18H512321AF
512-Mbit GDDR3
Electrical Characteristics
5.12
Table 38
Parameter
AC Timings ( HYB18H512321AF–12/14/16/20)
Timing Parameters (HYB18H512321AF–12/14/16/20)
CAS
Symbol
Limit Values
–16
Unit
–20
latency
–12
–14
min max min max min max min
max
Clock and Clock Enable
System frequency CL= 11
CL =10
3501) 800
3501) 700
3501) 650
3501) 550
3501) 500
3501) 700
3501) 650
3501) 600
3501) 500
3501) 450
fCK11
fCK10
fCK9
fCK8
fCK7
tCH
MHz
MHz
MHz
MHz
MHz
tCK
3501) 600
3501) 550
3501) 500
3501) 450
CL = 9
CL = 8
CL = 7
3501) 500
3501) 450
0.45
0.45
0.45
0.55
0.55
—
0.45
0.45
0.45
0.55
0.55
—
0.45
0.45
0.45
0.55
0.55
—
0.45
0.45
0.45
0.55
0.55
—
Clock high level width
Clock low level width
Minimum clock half period
tCL
tHP
tCK
tCK
2)
Command and Address Setup and Hold Timing
0.3
0.3
0.7
—
—
—
0.35
0.35
0.7
—
—
—
0.4
0.4
0.7
—
—
—
0.5
0.5
0.7
—
—
—
Address/Command input
tIS
ns
ns
tCK
setup time
Address/Command input hold tIH
time
Address/Command input
pulse width
tIPW
Mode Register Set Timing
Mode Register Set cycle time tMRD
Mode Register Set to READ
timing
3)4)
3)
6
—
—
6
—
—
6
—
—
6
—
—
tCK
tCK
12
12
12
12
tMRDR
Row Timing
Row Cycle Time
Row Active Time
ACT(a) to ACT(b) Command tRRD
period
32
21
8
—
—
—
30
18
7
—
—
—
27
17
6
—
—
—
23
14
5
—
—
—
tRC
tRAS
tck
tck
tck
5)
13
12
—
—
12
11
—
—
11
10
—
—
9
8
—
—
Row Precharge Time
Row to Column Delay Time for tRCDRD
Reads
tRP
tck
tck
tRCDWR(min) = tRCDRD(min) - (WL + 1) × tCK
Row to Column Delay Time for tRCDWR
tck
Writes
Column Timing
6)
7)
8)
2
6
—
—
2
5
—
—
2
5
—
—
2
4
—
—
CAS(a) to CAS(b) Command tCCD
tCK
tck
tCK
period
Write to Read Command
Delay
tRTW(min)= (CL + BL/2 +2 -WL)
Read to Write command delay tRTW
Write Cycle Timing Parameters for Data and Data Strobe
tWTR
WL– WL+ WL–
0.25 0.25 0.25
WL+ WL–
0.25 0.25
WL+ WL -
WL+
0.25
Write command to first WDQS tDQSS
tCK
0.25
0.25
latching transition
Data Sheet
92
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
