HYB18H512321AF
512-Mbit GDDR3
Electrical Characteristics
5.11
Operating Current Measurement Conditions
Table 37
Operating Current Measurement Conditions
Symbol Parameter/Condition
Operating Current - One bank, Activate - Precharge
IDD0
tCK=min(tCK), tRC=min(tRC)
Databus inputs are SWITCHING; Address and control inputs are SWITCHING, CS = HIGH between
valid commands.
IDD1
Operating Current - One bank, Activate - Read - Precharge
One bank is accessed with tCK=min(tCK), tRC=min(tRC), CL = CL(min), Address and control inputs are
SWITCHING;
CS = HIGH between valid commands. Iout=0mA
IDD2P
IDD2F
Precharge Power-Down Standby Current
All banks idle, power-down mode, CKE is LOW, tCK=min(tCK), Data bus inputs are STABLE (HIGH).
Precharge Floating Standby Current
All banks idle; CS is HIGH, CKE is HIGH, tCK=min(tCK); Address and control inputs are SWITCHING;
Data bus input are STABLE (HIGH).
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
Precharge Quiet Standby Current
CS is HIGH, all banks idle, CKE is HIGH, tCK=min(tCK), Address and other control inputs STABLE
(HIGH), Data bus inputs are STABLE (HIGH).
Active Power-Down Standby Current
One bank active, CKE is LOW, Address and control inputs are STABLE (HIGH); Data bus inputs are
STABLE (HIGH); standard active power-down mode.
Active Standby Current
One bank active, CS is HIGH, CKE is HIGH, tRAS= tRAS,max, tCK=min(tCK); Address and control inputs
are SWITCHING; Data bus inputs are SWITCHING.
Operating Current - Burst Read
One bank active; Continuous read bursts, CL = CL(min); tCK=min(tCK); tRAS= tRAS,max; Address and
control inputs are SWITCHING; Iout = 0 mA.
Operating Current - Burst Write
One bank active; Continuous write bursts; tCK=min(tCK); Address and control inputs are SWITCHING;
Data bus inputs are SWITCHING.
Burst Auto Refresh Current
Refresh command at tRFC=min(tRFC); tCK=min(tCK); CKE is HIGH, CS is HIGH between all valid
commands; Other command and address inputs are SWITCHING; Data bus inputs are SWITCHING.
Distributed Auto Refresh Current
tCK=tCKmin; Refresh command every tREFI; CKE is HIGH, CS is HIGH between valid commands; Other
command and address inputs are SWITCHING; Data bus inputs are SWITCHING.
Self Refresh Current
CKE ≤ max(VIL), external clock off, CK and CK LOW; Address and control inputs are STABLE (HIGH);
Data Bus inputs are STABLE (HIGH).
IDD7
Operating Bank Interleave Read Current
1. All banks interleaving with CL = CL(min); tRCD = tRCDRD(min); tRRD = tRRD(min); Iout=0 mA; Address
and control inputs are STABLE (HIGH) during DESELECT; Data bus inputs are SWITCHING.
2: Timing pattern: tbd.
1. 0 °C ≤ Tc ≤ 85 °C
2. Data Bus consists of DQ, DM, WDQS.
Data Sheet
90
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
