HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.6.6
Write followed by DTERDIS
0
1
2
3
4
5
6
7
8
9
10
CLK#
CLK
WR
B/C
DTD
DES
DES
DES
DES
DES
DES
DES
DES
DES
CL = 7
WL = 3
WDQS
DQ
D0
D1
D2
D3
WR
B/C
N/D
DTD
DES
DES
DES
DES
DES
DES
DES
DES
CL = 7
WL = 4
WDQS
DQ
D0
D1
D2
D3
B / C: Bank / Column address
WR: WRITE
DTD: DTERDIS
WL:
CL:
Write Latency
CAS Latency
Deselect
DES:
N/D:
D#:
Data to B / Cx
NOP or Deselect
Com.: Command
Don't Care
Data Termination Off
Addr.: Address B / C
Figure 33 Write Command followed by DTERDIS
1. Shown with nominal value of tDQSS
.
2. WDQS can only transition when data is applied at the chip input and during pre- and postambles.
3. A margin of one clock has been introduced in order to make sure that the data termination are still on when
the last Write data reaches the memory.
4. The minimum distance between Write and DTERDIS is one clock.
Data Sheet
52
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
