HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.6.7
Write with Autoprecharge followed by Read / Read with Autoprecharge
0
1
2
3
4
5
6
7
8
9
10
CLK#
CLK
RD
Com.
WR/A
B/C
N/D
DES
DES
DES
DES
DES
DES
DES
DES
RD/A
A9,
B/C
A2-A7
A8
t
WTR
t
t
RP
WR/A
WL = 3
WDQS
DQ
D0
D1
D2
D3
Begin of Autoprecharge
RD
Com.
WR/A
B/C
N/D
DES
DES
DES
DES
DES
DES
DES
DES
RD/A
A9,
B/C
A2-A7
A8
t
WTR
tRP
t
WR/A
WL = 4
WDQS
DQ
D0
D1
D2
D3
Begin of Autoprecharge
Com.: Command
Addr.: Address B / C
WL: Write Latency
Don't Care
B / C: Bank / Column address
WR/A: WRITE with Autoprecharge
RD RD/A: READ or
READ with Autoprecharge
D#:
DES: Deselect
N/D: NOP or Deselect
Data to B / Cx
0: RD, 1: RD/A
Figure 34 Write with Autoprecharge followed by Read or Read with Autoprecharge on another bank.
1. Shown with nominal value of tDQSS
.
2. The RD command is only allowed for another activated bank.
3. tWR/A is set to 4 in this example.
4. WDQS can only transition when data is applied at the chip input and during pre- and postambles.
Data Sheet
53
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
