HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.6.8
Write followed by Precharge on same bank.
0
1
2
3
4
5
6
7
8
9
10
CLK#
CLK
WR
B/C
N/D
DES
DES
DES
DES
DES
DES
DES
PRE
B
DES
tRP
WL = 3
tWR
WDQS
DQ
D0
D1
D2
D3
WR
B/C
N/D
DES
DES
DES
DES
DES
DES
DES
DES
PRE
B
tRP
WL = 4
tWR
WDQS
DQ
D0
D1
D2
D3
N/D: NOP or Deselect
DES: Deselect
Com.: Command
B / C: Bank / Column address
WR:
PRE:
Dx#:
Dy#:
WRITE
PRECHARGE
Data to B / Cx
Data to B / Cy
Addr.: Address B / C
WL:
Write Latency
Don't Care
Figure 35 Write followed by Precharge on same Bank
1. Shown with nominal value of tDQSS
2. WR and PRE commands are to same bank.
3. tRAS requirement must also be met before issuing PRE command.
4. WDQS can only transition when data is applied at the chip input and during pre- and postambles.
.
Data Sheet
54
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
