HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.6.4
Write with Autoprecharge
0
1
2
3
4
5
6
7
8
9
10
11
CLK#
CLK
Com.
WR/A
B/C
N/D
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
A9,
A7-A2
A8
WL = 3
tWR/A =4
WDQS
DQ
tRP
D0
D1
D2
D3
Begin of
tRAS MIN
satisfied
Autoprecharge
WL = 4
tWR/A =4
WDQS
DQ
tRP
D0
D1
D2
D3
Begin of
Autoprecharge
tRAS MIN
satisfied
Com.: Command
B / C: Bank / Column address
Addr.: Address B / C
WR/A: WRITE with auto-precharge
Data to B / C
WL:
Write Latency
Don't Care
D#:
DES: Deselect
N/D: NOP or Deselect
Figure 31 Write with Autoprecharge
1. Shown with nominal value of tDQSS
.
2. tWR/A starts at the first rising edge of CLK after the last valid edge of WDQS.
3. tRP starts after tWR/A has been expired.
4. When issuing a WR/A command please consider that the tRAS requirement also must be met at the beginning
of tRP
5. tWR/A * tCYC ≥ tWR
6. WDQS can only transition when data is applied at the chip input and during pre- and postambles.
.
.
Data Sheet
50
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
