HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.6.3.2
Bursts with Gaps
0
1
2
3
4
5
6
7
8
9
10
CLK#
CLK
Com
.
WR
N/D
N/D
WR
N/D
DES
DES
DES
DES
DES
DES
Addr.
B/Cx
B/Cy
WL = 3
WDQS
DQ
Dx0 Dx1 Dx2 Dx3
Dy0 Dy1 Dy2 Dy3
WL = 4
WDQS
DQ
Dx0 Dx1 Dx2 Dx3
Dy0 Dy1 Dy2 Dy3
Com.: Command
Addr.: Address B / C
WL: Write Latency
DES: Deselect
N/D: NOP / Deselect
B / Cx: Bank / Column address x
B / Cy: Bank / Column address y
WR:
Dx#:
Dy#:
WRITE
Data to B / Cx
Data to B / Cy
Don't Care
Figure 30 Consecutive Write Bursts with Gaps
1. Shown with nominal value of tDQSS
2. The second WR command may be either for the same bank or another bank.
3. WDQS can only transition when data is applied at the chip input and during pre- and postambles.
.
Data Sheet
49
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
