HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.7
Reads (RD)
4.7.1
Read - Basic Information
its first rising edge (RD preamble tRPRE). After the last
falling edge of RDQS a postamble of tRPST is
performed.
CLK#
CLK
tAC is the time between the positive edge of CLK and
the appearance of the corresponding driven read data.
The skew between RDQS and the crossing point of
CLK/CLK is specified as tDQSCK. tAC and tDQSCK are
defined relatively to the positive edge of CLK. tDQSQ is
the skew between a RDQS edge and the last valid data
edge belonging to the RDQS edge. tDQSQ is derived at
each RDQS edge and begins with RDQS transition and
ends with the last valid transition of DQs. tQHS is the
data hold skew factor and tQH is the time from the first
valid rising edge of RDQS to the first conforming DQ
going non-valid and it depends on tHP and tQHS. tHP is
the minimum of tCL and tCH. tQHS is effectively the time
from the first data transition (before RDQS) to the
RDQS transition. The data valid window is derived for
each RDQS transition and is defined as tQH minus
CKE
CS#
RAS#
CAS#
WE#
A2-A7, A9
CA
A0, A1
A10-A11
tDQSQ
.
After completion of a burst, assuming no other
commands have been initiated, data will go HIGH and
RDQS will go HIGH. Back to back RD commands are
possible producing a continuous flow of output data.
There has to be one NOP cycle between back to back
RD commands.
A8
AP
BA
AP: AutoPrecharge
CA: Column Address
BA: Bank Address
BA0-BA2
Don't Care
Figure 36 Read Command
Any RD burst may be followed by a subsequent WR
command. The minimum required number of NOP
commands between the RD command and the WR
command (tRTW) depends on the programmed Read
latency and the programmed Write latency
Read bursts are initiated with a RD command, as
shown in Figure 36. The column and bank addresses
are provided with the RD command and Autoprecharge
is either enabled or disabled for that access. The length
of the burst initiated with a RD command is 4 or 8.
There is no interruption of RD bursts. The two least
significant start address bits are ’Don’t Care’.
If Autoprecharge is enabled, the row being accessed
will start precharge at the completion of the burst. The
begin of the internal Autoprecharge will always be one
cycle after tRAS(min) is met.
During RD bursts the memory device drives the read
data edge aligned with the RDQS signal which is also
driven by the memory. After a programmable CAS
latency of 7, 8. 9 or 10 the data is driven to the
controller. RDQS leaves HIGH state one cycle before
tRTW(min)= (CL+4-WL).
Chapter 4.7.7 shows the timing requirements for RD
followed by a WR with some combinations of CL and
WL.
A RD may also be followed by a PRE command. Since
no interruption of bursts is allowed the minimum time
between a RD command and a PRE is two clock cycles
as shown in Chapter 4.7.8.
All timing parameters are defined with controller
terminations on.
Data Sheet
55
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
