HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.6.3
Write - Consecutive Bursts
Gapless Bursts
4.6.3.1
0
1
2
3
4
5
6
7
8
9
CLK#
CLK
Com.
Addr.
WR
N/D
WR
N/D
DES
DES
DES
DES
DES
DES
B/Cx
B/Cy
WL = 3
WDQS
DQ
Dx0 Dx1 Dx2 Dx3 Dy0 Dy1 Dy2 Dy3
WL = 4
WDQS
DQ
Dx0 Dx1 Dx2 Dx3 Dy0 Dy1 Dy2 Dy3
Dx#:
Dy#:
Data to B / Cx
Data to B / Cy
WR:
WRITE
B / Cx: Bank / Column address x
B / Cy: Bank / Column address y
DES: Deselect
Com.: Command
N/D:
NOP / Deselect
WL:
Write Latency
Addr.: Address B / C
Don't Care
Figure 29 Gapless Write Bursts
1. Shown with nominal value of tDQSS
.
2. The second WR command may be either for the same bank or another bank.
3. WDQS can only transition when data is applied at the chip input and during pre- and postambles.
Data Sheet
48
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
