HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.6.5
Write followed by Read
0
1
2
3
4
5
6
7
8
9
CLK#
CLK
WR
B/C
N/D
DES
DES
DES
DES
DES
DES
RD
N/D
B/C
WL = 3
tWTR
WDQS
DQ
D0
D1
D2
D3
WR
B/C
N/D
DES
DES
DES
DES
DES
DES
DES
RD
B/C
WL = 4
tWTR
WDQS
DQ
D0
D1
D2
D3
B / C: Bank / Column address
D#:
Data to B / Cx
WR:
RD:
WRITE
READ
Com.: Command
Addr.: Address B / C
DES: Deselect
WL:
Write Latency
N/D: NOP / Deselect
Don't Care
Figure 32 Write followed by Read
1. Shown with nominal value of tDQSS
.
2. The RD command may be either for the same bank or another bank.
3. WDQS can only transition when data is applied at the chip input and during pre- and postambles.
Data Sheet
51
Rev. 1.73, 2005-08
05122004-B1L1-JEN8