September 2006
rev 0.4
PCS2I99447
APPLICATIONS INFORMATION
CCLK or
PCLK
3.0
CLK _ STOP
Q0 to Q11
OutA
OutB
tD = 3.9386
2.5
2.0
1.5
tD = 3.8956
Figure 1. Output Clock Stop (CLK_STOP)
Timing Diagram
In
Driving Transmission Lines
The PCS2I99447 clock driver was designed to drive high
speed signals in terminated transmission line
1.0
0.5
0
a
environment. To provide the optimum flexibility to the
user, the output drivers were designed to exhibit the
lowest impedance possible. With an output impedance of
17ꢀ (VCC=3.3V), the outputs can drive either parallel or
series terminated transmission lines. In most high
performance clock networks, point–to–point distribution of
signals is the method of choice. In a point–to–point
scheme, either series terminated or parallel terminated
transmission lines can be used. The parallel technique
terminates the signal at the end of the line with a 50ꢀ
resistance to VCC÷2.
2
4
6
8
10
12
14
TIME (nS)
Figure 3. Single versus Dual Line Termination
Waveforms
The waveform plots in Figure 3 “Single versus Dual Line
Termination Waveforms” show the simulation results of
an output driving a single line versus two lines. In both
cases, the drive capability of the PCS2I99447 output
buffer is more than sufficient to drive 50ꢀ transmission
lines on the incident edge. Note from the delay
measurements in the simulations a delta of only 43pS
exists between the two differently loaded outputs. This
suggests that the dual line driving need not be used
exclusively to maintain the tight output–to–output skew of
the PCS2I99447. The output waveform in Figure 3
“Single versus Dual Line Termination Waveforms” shows
a step in the waveform; this step is caused by the
impedance mismatch seen looking into the driver. The
parallel combination of the 33Ω series resistor plus the
output impedance does not match the parallel
combination of the line impedances. The voltage wave
launched down the two lines will equal:
PCS2I99447
OUTPUT BUFFER
Z0=50ꢀ
RS=33ꢀ
17ꢀ
PCS2I99447
Z0=50ꢀ
RS=33ꢀ
RS=33ꢀ
OUTPUT BUFFER
17ꢀ
Z0=50ꢀ
Figure 2. Single versus Dual Transmission
Lines
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the PCS2I99447 clock driver. For the series
terminated case, however, there is no DC current draw;
thus, the outputs can drive multiple series terminated
lines. Figure 2 “Single versus Dual Transmission Lines”
illustrates an output driving a single series terminated line
versus two series terminated lines in parallel. When taken
to its extreme, the fanout of the PCS2I99447 clock driver
is effectively doubled due to its capability to drive multiple
lines at VCC=3.3V.
VL = VS ( Z0 (RS+R0 +Z0))
Z0 = 50Ω || 50Ω
RS = 33Ω || 33Ω
R0 = 17Ω
VL = 3.0 ( 25 ÷ (16.5+17+25)
= 1.28V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.5V. It will then increment
towards the quiescent 3.0V in steps separated by one
3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer
6 of 14
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
