September 2006
rev 0.4
PCS2I99447
Block Diagram
Q0
Q1
0
CLK
CCLK0
CCLK1
STOP
1
VCC
VCC
Q2
CLK_SEL
Q3
Q4
SYNC
CLK_STOP
Q5
Q5
Q6
Q7
VCC
OE
(All input resistors have a value of 25KΩ)
Pin Configuration
24 23
22
21
20
19
18
17
GND
Q2
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
GND
Q6
VCC
Q1
VCC
Q7
PCS2I99447
GND
Q0
GND
Q8
VCC
GND
VCC
GND
1
2
3
4
5
6
7
8
3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer
2 of 14
Notice: The information in this document is subject to change without notice.