September 2006
rev 0.4
PCS2I99447
Table 7. DC Characteristics (VCC = 2.5V ± 5%, TA = -40°C to +85°C)
Symbol
VIH
Characteristics
Min
1.7
-0.3
1.8
Typ
Max
VCC + 0.3
0.7
Unit
V
V
V
V
Condition
LVCMOS
Input High Voltage
VIL
VOH
VOL
ZOUT
IIN
ICCQ
Input Low Voltage
LVCMOS
Output High Voltage
Output Low Voltage
Output Impedance
IOH =-15 mA1
IOL = 15 mA
0.6
19
Ω
Input Current2
±300
2.0
mA
mA
VIN = VCC or GND
All VCC Pins
Maximum Quiescent Supply Current3
Note: 1.The PCS2I99447 is capable of driving 50ꢀ transmission lines on the incident edge. Each output drives one 50ꢀ parallel terminated transmission line to
a termination voltage of VTT. Alternatively, the device drives one 50ꢀ series terminated transmission lines per output (VCC=2.5V).
2. Inputs have pull-down or pull-up resistors affecting the input current.
3. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
Table 8. AC Characteristics (VCC = 2.5V ± 5%, TA = -40°C to +85°C)1
Symbol
fref
fmax
fP,REF
tr, tf
tPLH/HL
tPLZ, HZ
tPZL, ZH
Characteristics
Min
0
0
Typ
Max
350
350
Unit Condition
Input Frequency
Output frequency
MHz
MHz
nS
Reference Input Pulse Width
CCLK0, CCLK1 Input Rise/Fall Time
1.4
1.02
4.4
11
nS
nS
nS
nS
0.7 to 1.7V
Propagation Delay
Output Disable Time
Output Enable Time
CCLK0 or CCLK1 to any Q
1.7
11
tS
tH
0.0
1.0
nS
nS
Setup Time
Hold Time
CCLK0 or CCLK1 to CLK_STOP3
CCLK0 or CCLK1 to CLK_STOP3
tsk(O)
tsk(PP)
Output-to-Output Skew
Device-to-Device Skew
150
2.7
pS
nS
Output Pulse Skew4
Output Duty Cycle
tSK(P)
DCQ
pS
%
200
55
1.0
DCREF=50%
0.6 to 1.8V
fQ<350 MHz
45
0.1
50
tr, tf
tJIT(CC)
Output Rise/Fall Time
Cycle-to-cycle jitter
nS
pS
TBD
RMS (1 σ)
Note:1. AC characteristics apply for parallel output termination of 50ꢀ to VTT
.
2. Violation of the 1.0 nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse
width, output duty cycle and maximum frequency specifications.
3. Setup and hold times are referenced to the falling edge of the selected clock signal input.
4. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |.
3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer
5 of 14
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
