September 2006
rev 0.4
PCS2I99447
VCC
VCC ÷2
GND
CCLK
VCC
VCC ÷2
QX
GND
tP(LH)
tP(HL)
Figure 6. Propagation Delay (tPD
) Test Reference
VCC
VCC ÷2
GND
VCC
VCC ÷2
GND
CCLK
VCC
VCC ÷2
VCC
VCC ÷2
GND
QX
GND
tSK(LH)
tSK(HL)
tP(LH)
tP(HL)
The pin-to-pin skew is defined as the worst case
t
SK(P) =| tPHL - tPHL |
difference in propagation between any similar delay path
within a single device
Figure 8. Output Pulse Skew (tSK(P)
Test
Figure 7. Output–to–Output Skew tSK(LH, HL)
VCC
VCC ÷2
GND
VCC = 3.3V VCC = 2.5V
2.4
0.5
1.8V
0.6V
tP
tR
T0
tF
DC (tP ÷T0 Χ 100%)
Figure 10. Output Transition Time Test Reference
The time from the output controlled edge to the
non-controlled edge, divided by the time output
controlled edge, expressed as a percentage.
Figure 9. Output Duty Cycle (DC)
VCC
VCC ÷2
GND
CCLK
VCC
VCC ÷2
CLK_STOP
TJIT(CC) = |TN -TN + 1|
GND
TN
TN + 1
tH
tS
The variation in cycle time of a single between adjacent
cycles, over a random sample of adjacent cycle pairs
Figure 11. Cycle–to–Cycle Jitter Reference
Figure 12. Setup and Hold Time (tS
, tH
) Test Reference
3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer
8 of 14
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
