September 2006
rev 0.4
PCS2I99447
round trip delay (in this case 4.0ns). Since this step is
well above the threshold region it will not cause any false
clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines,
PCS2I99447
Z0=50ꢀ
RS16ꢀ
OUTPUT BUFFER
17ꢀ
Z0=50ꢀ
RS=16ꢀ
the situation in Figure
4
“Optimized Dual Line
Termination” should be used. In this case, the series
terminating resistors are reduced such that when the
parallel combination is added to the output buffer
impedance the line impedance is perfectly matched.
17Ω + 16Ω ║ 16Ω = 50Ω ║ 50Ω
25Ω = 25Ω
Figure 4. Optimized Dual Line Termination
The Following Figures Illustrate the Measurement Reference for the PCS2I99447 Clock Driver Circuit
PCS2I99447
Z0=50Ω
Z0=50Ω
Pulse
Generator
Z=50Ω
RT=50Ω
RT=50Ω
TT
VTT
Figure 5. CCLK PCS2I99447 AC Test Reference for Vcc = 3.3V and Vcc = 2.5V
3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer
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Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
