September 2006
rev 0.4
PCS2I99447
Table 1. Function Table
Control
CLK_SEL
OE
Default
0
1
1
1
CLK0 input selected
CLK1 input selected
Outputs disabled (high–impedance state)1
Outputs enabled
1
Outputs synchronously stopped in logic low state
Outputs active
CLK_STOP
Note: 1. OE = 0 will high–impedance tristate all outputs independent on CLK_STOP
Table 2. Pin Configuration
Pin #
Pin Name
I/O
Type
Function
3
4
2
CCLK0
Input
Input
Input
LVCMOS Clock signal input
CCLK1
CLK_SEL
LVCMOS Alternative clock signal input
LVCMOS Clock input select
5
Input
LVCMOS Clock output enable/disable
CLK_STOP
OE
Output enable/disable
LVCMOS
6
Input
Output
Supply
(high–impedance tristate)
11,13,15,19,21,23,26,28,30
Q0 – Q8
LVCMOS Clock outputs
Negative power supply (GND) for
1,8,9,12,16,17,20,24,25,29,32 GND
Ground
Output and Core
Positive power supply for I/O and
core. All VCC pins must be connected
7,10,14,18,22,27,31
VCC
Supply
VCC
to the positive power supply for
correct operation
Table 3. General Specifications
Symbol
VTT
MM
HBM
LU
Characteristics
Output termination voltage
ESD protection (Machine model)
ESD protection (Human body model)
Latch-up immunity
Min
Typ
Max
Unit
V
V
Condition
VCC ÷2
200
2000
200
V
mA
pF
pF
CPD
CIN
Power dissipation capacitance
Input capacitance
10
4.0
Per output
Inputs
Table 4. Absolute Maximum Ratings1
Symbol
VCC
VIN
VOUT
IIN
Characteristics
Min
-0.3
-0.3
-0.3
Max
Unit
V
V
Condition
Supply Voltage
3.9
VCC + 0.3
VCC + 0.3
±20
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage temperature
V
mA
mA
°C
±50
125
IOUT
TS
-65
Note: 1.These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer
3 of 14
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
