RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
7.4 Performance Counters
The RM7965A supports two CP0 performance-counter registers with the PerfCount and
PerfControl registers. The PerfCount register is a 64-bit register divided into two independent
32-bit counters, PerfCounter0, PerfCounter1. The counters can be written to by software to
initialize event monitoring, and they generate a performance-counter interrupt when the most
significant bit in either counter (bit 63 in Counter 2, and bit 31 in Counter 1) is set.
The PerfControl register is a 32-bit register containing two 5-bit fields used to select one of
twenty-four event types counted by each counter, as well as a handful of bits which control the
overall counting function. Note that only one event type can be counted per counter at a time,
and that counting can occur for user code, kernel code or both. The event types and control bits
are listed in Table 18.
Table 18 Performance Counter Control
PerfControl
Field
Description
4:0
Event Type
00:
01:
02:
03:
04:
05:
06:
07:
08:
09:
0A:
0B:
0C:
0D:
0E:
0F:
10:
11:
12:
13:
14:
15:
Clock cycles
Total instructions issued (Integer and Floating Point)
Floating-point instructions issued (any COP1 or COP3).
Integer instructions issued (no COP1 or COP3).
Load instructions issued
Store instructions issued
Dual issued instruction pairs
Branch mispredictions
External Cache Misses
Stall cycles
Secondary cache misses
Instruction cache misses
Data cache misses
Data TLB misses
Instruction TLB misses
Joint TLB instruction misses
Joint TLB data misses
Branches taken
Branches issued
Secondary cache writebacks
Data cache writebacks
Data cache miss stall cycles (A stall occurs when the data cache is processing
two misses and a third miss occurs).
16:
17:
18:
19:
1A:
1B:
1C:
1D:
1E:
Cache misses (all caches).
FP possible exception cycles
Slip Cycles due to multiplier busy
Coprocessor 0 slip cycles
Slip cycles due to pending non-blocking loads
Stall cycles due to full Write buffer
Stall cycles due to Cache instruction
Unused
Stall cycles due to pending non-blocking loads - stall start of exception
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Document No.: PMC-2100294, Issue 2
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