RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
Name
Size Field
Description
SysConfig[1:0]
2
29:28
System configuration mode bits, to Config register.
Value software visible in Config[21:20].
Enables the core on-chip secondary caches.
OCacheEn
OTClrEn
1
30
0: OCache Disabled (OCacheDisabled)
1: OCache Enabled (OCacheEnabled)
1
31
Enables the Ocache tag clear machine on cold reset.
When OTClrEn = 1, the following will be cleared: L2 Tag, L1
DTag, L1 Itag, L1 Dcache, L1 Icache and BranchPredict RAM.
0: OTag clear machine disabled (OTClrDisabled)
1: OTag clear machine enabled (OTClrEnabled)
ParChkDis
TLB64Ent
1
1
32
33
Disables all parity checking processor-wide.
0: Par check enabled (ParChkEnabled)
1: Par check disabled (ParChkDisabled)
Enables a larger JTLB size on the core.
0: 48 entry JTLB (TLB48Entry)
1: 64 entry JTLB (TLB64Entry)
HitShrFtch
1
1
34
35
Reserved, must be set to 0.
MIPS64Compat
MIPS 64 compatibility mode. Reorganizes CP0 to be MIPS 64
compatible.
0: MIPS IV compatibility (PMCCompat)
1: MIPS 64 compatibility (MIPS64Compat)
PowerSave
1
4
2
36
Reserved, must be set to 0.
Reserved, must be set to 0.
CorePbRsvd[3:0]
CkPdAlgn[1:0]
40:37
42:41
Adjusts the MasterClock pad delay matching network. Reduces
the swing on the internal MasterClock equivalent signal fed back
to PLLs for matching the external MasterClock swing. These
mode bits are for HSTL only. They should be left at 00 in the
LVTTL mode.
00: No swing control - Full swing (0–1.2V) - default setting for
cy2210 clock driver (common mode voltage - 0.6V)
01: MasterClock (internal f/b signal) swing matched for external
MasterClock swing of < 0.5V
10: External MasterClock swing is 0.5–0.4V
11: External MasterClock swing < 0.4V
Default setting 00.
PLLDis
1
1
43
44
Enables or disables the PLL.
0: Enabled (PLLEnabled)
1: Disabled (PLLDisabled)
DivMa2Core
MasterClock divide by two for PLL.
0: Divide by one (DivBy1)
1: Divide by two (DivBy2)
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
50
PMC [ PMC-SIERRA, INC ]
