RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
7.3 Test/Breakpoint Registers
To facilitate hardware and software debugging, the RM7965A incorporates a pair of Test/Break-
point, or Watch registers, called Watch1 and Watch2. Each Watch register can be separately
enabled to watch for a load address, a store address, or an instruction address. All address
comparisons are done on virtual addresses. An associated register, WatchMask, allows either or
both of the Watch registers to compare against an address range rather than a specific address.
The range granularity is limited to a power of two.
When enabled, a match of either Watch register results in an exception. If the Watch is enabled
for a load or store address then the exception is the Watch exception as defined for the R4000 by
Cause exception code 23. If the Watch is enabled for instruction addresses then a Instruction
Watch exception is taken and the Cause exception code is 16. The Watch register that caused the
exception is indicated by Cause bits 25:24. Table 17 summarizes a Watch operation.
If the DBEN bit is set, an address comparison will cause a Debug Exception, which vectors to
0xbfc00240.
Table 17 Watch Registers
Register
Bit Field/Function
63:59
58
57
56
55
54
53:40
39:2
1
0
Watch 1
Caddr
[63:59]
Caddr
[39:2]
0
0
DBEN
DBOut
Store
Load
Inst
Rsvd
0
0
Caddr
[39:2]
Watch 2
Caddr
DBEN
DBOut
Store
Load
Inst
Rsvd
[63:59]
Watch
Mask
Mask
Watch2
Mask
Watch
1
Mask
[63:59]
Mask
[39:2]
Reserved
Note:
1. The W1 and W2 bits of the Cause register indicate which Watch register caused a particular Watch
exception.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
45
PMC [ PMC-SIERRA, INC ]
