RM7965A-900UI 900 MHz 64-bit Microprocessor Data Sheet
7
Integrated Debug
The E9000 has extended the debugging features found on the RM7000 and has added EJTAG
Debugging and a 64-entry Branch Inst. Trace Buffer.
7.1 EJTAG Debugging
The EJTAG 2.5 standard is implemented to allow access to the processor subsystem through the
EJTAG port. This allows an emulator to be plugged into the EJTAG port to single-step, modify
memory and registers, and to provide hardware breakpoints. EJTAG mode on the RM7965A is
selected by using the JTAGSEL pin. When JTAGSEL is set to “1”, JTAG is selected. When
JTAGSEL is set to “0”, EJTAG is selected.
A new exception vector at 0xBFC0_0240 is allocated for EJTAG Debugging. In addition, a
Debug Register Section at 0xff20_0000 and a Debug Memory Section at 0xff30_0000 to
0xff3f_ffff is implemented.
Two new instructions have been added to support on-chip debugging. A Software Debug Break-
Point (SDBBP) allows breakpoints to be taken by the code. Once in the debug exception
handler, the Debug Return (DERET) instruction is used to exit the debug exception handler.
Three new CP0 registers have been added in the CP0 system address space to support EJTAG
functionality. The EJTAG_Debug register at CP0_23 serves as the control and status register.
The EJTAG_DEPC register at CP0_24 serves as the same purpose for the debug exception as
the EPC register does for general exceptions. The EJTAG_DESave register at CP0_31 is used as
a general purpose “save area” for EJTAG debug support. See Figure 5.
7.2 Trace Buffer
A Trace buffer is implemented on the processor core to allow tracing of instruction flow. The
trace buffers are 64-entries deep and capture branch addresses and branch target addresses so
that the precise flow of instruction execution can be reconstructed. Using this sophisticated
compression technique, the reconstructed instruction length can be many times larger than the
trace buffer length. The trace buffer can trigger an interrupt when it is ¼, ½, ¾ or completely
full. If no interrupt is set, the buffer will wrap around. The trace buffer shares the IP13 interrupt
with the Performance Counters.
To support the Trace Buffer, 3 new CP0 register are implemented in the CP0 control address
space. The Trace Buffer Control and Status (TB CSR) register is at CP0_22 and performs the
function its name suggests. The Trace Buffer Index (TB IDX) register is at CP0_24 and is the
address into the trace buffer. The Trace Buffer Out (TB Out) register is at CP0_23 and contains
data from the read at the index given in the TB IDX register.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2100294, Issue 2
44
PMC [ PMC-SIERRA, INC ]
